Oticon explained that it needed to add features to the next generation DSP without increasing the design area and the power consumption. To prevent the routing congestion caused by the added functionality, Oticon said it deployed the congestion optimizations in Synopsys' Design Compiler Graphical during RTL synthesis. The result, Oticon claimed, was an easy to route netlist and predictable design closure ahead of schedule.

"As we enhanced the feature set of our next generation DSP, we saw severe routing congestion due to tight chip area requirements," commented Mogens Balsby, director of Silicon Engines at Oticon. "By utilizing Design Compiler Graphical's congestion optimizations, we eliminated this routing congestion upfront without having to increase our chip area, and taped out successfully ahead of schedule."

Back in 2008, Synopsys extended Design Compiler topographical technology with the introduction of Design Compiler Graphical synthesis product aimed at helping RTL designers avoid wire-routing congestion problems that occur during detailed route.

Design Compiler Graphical predicts circuit congestion "hot spots" early in the design flow, provides designers with visualization of the congested circuit regions and performs synthesis optimizations to minimize congestion in these areas, the company then claimed.