Flexibility in choosing the right operational parameters of the memory subsystem is one of the critical success factors in the design of an electronic application.

The operating frequency of the memory, for example, must be carefully selected depending from many external factors. It is strongly related to the capacitive load of the system, to the intrinsic performance of the chips and to the complexity and layout of the printed circuit board. Normally, designers try to maximize the speed of the system. However, at high operating frequencies it may be rather difficult to fine tune and optimize the electrical parameters: the high noise levels across the board must be taken into account and it is not easy to reduce the parasitic capacitance of wires and signal paths. In this case, it is very convenient to have the flexibility to decrease the “strength” of the output drivers of the memory chip. 

Another important option is the optimization of the instruction execution time: sometimes, there is the need to reduce the number of the so-called “dummy clock cycles” in order to achieve the required memory data throughput.

The design engineer must have the flexibility to adjust the electrical and timing parameters of the memory subsystem in order to maximize the overall performance of his system.

 

A new generation of SPI Flash memories
There are other areas where flexibility in the memory subsystem is very important. During the testing process of an application board, for example, the microcontroller which runs the system must issue a full set of commands to correctly stimulate the memory chips and fully check their functionality. This is no longer needed when the system is operating under normal conditions and only a reduced set of commands is used. 

A new generation of non-volatile memories is emerging, based on a unique architecture providing the right level of cost-efficient flexibility: SPI (Serial Peripheral Interface) Flash memories with configuration registers. Traditional SPI Flash memories exchange instructions, addresses and data with the external world through a serial bus which may use from one to four different wires. The normal operation of a standard SPI memory requires that an instruction (such as read, or write, or erase) is sent to the device via the bus, followed by an address and by the relevant data to be read or written from/to the memory.

SPI Memories have one distinctive advantage: a low pin count (8 or 16 pins, depending from the format of the package) for every density size. A small package with only few pins not only lowers the overall application cost, but also simplifies the layout of the printed circuit board. It allows the upgrade of the firmware without any changes in the system's architecture, decreasing the overall time and money spent in the development phase. The evolution of technologies, architectures and the intrinsic low cost of SPI Flash memories have fuelled their growth in the market of digital consumer systems as a replacement of traditional parallel Flash memories, whenever the performance requirements are met.

 

Store & Download versus XiP

SPI Flash Memories are synchronous devices traditionally used in a “store & download” configuration; for example to store the boot code in a Personal Computer. In this case, when the PC is powered up, the code is downloaded into the working RAM of the computer mostly using read instructions. In this typical “store & download” application, the memory should be optimized for read operations and for the download of the boot program at system power up.  In other fast growing applications such as optical disk drives, automotive systems, Bluetooth peripherals, set-top boxes and modems, the new generations of SPI Flash memories allow the control processor to execute the program code directly from the non-volatile memory and avoid the time-consuming process required to download the code into the high-speed volatile memory.

These are the so-called XiP (eXecute In Place) applications where the serial Flash must show some sort of “random access” emulation, i.e. the possibility to access its content without previously sending instructions, at the maximum possible throughput.

The request for the new “XiP” features will push the designers of memory architectures towards flexible hybrid memory subsystems. The devices will have the possibility to be managed as standard serial components using a JEDEC defined protocol based on a sequence of commands, addresses and data sent over a single wire (or up to four wires, in the case of quadruple I/O protocols). However, they will also work in “XiP” mode with “random access” emulation and no commands.

 

Choosing the right memory architectures

The introduction of volatile and non-volatile configuration registers in the last generation of SPI Flash memories provides the right level of flexibility to fit the different application needs of the most advanced platforms. Configuration registers give the final user the capability to define the behavior of the memory subsystem according to his requirements. The typical structure of an SPI memory with configuration registers is described in figure 1.

In a standard SPI Flash memory (with no configuration registers) commands are sent directly to an internal register that works as an instruction decoder and interacts with the status registers and with the internal state machine. After every power-on sequence, the standard (legacy) SPI memory will only accept commands: read, program and erase.

In the case of SPI architectures with configuration registers, the behavior may change. By default, the memory will behave as a normal legacy product. But the user can configure the registers according to his needs.  The configuration registers may be used for different purposes. They may define the strength of the output drivers of the device, the number of dummy clock cycles, and many other conditions such as XiP vs. store & download mode of operation.

 

Volatile and non-volatile configuration registers

The N25Q family of SPI Flash Memories from Numonyx offers two different types of configuration registers: volatile and non-volatile (table 1). After the system startup phase, the memory will behave according to the parameters stored in the non-volatile configuration registers.

The volatile configuration registers can be used to modify the behavior of the device, at any time, or during the testing phase of the application to fully check the functionality of the board and of the memory subsystem, for example changing the number of dummy clock cycles and/or increasing the strength of the output buffers in order to find the best match with the external load conditions and with all the other environmental parameters. Once the best setup has been defined, the related information may be stored in the non-volatile configuration registers, ready to be used the next time the system is restarted. So the final setup of the device can be completely different from the one used during the testing phase.

For example, the SPI Flash memory may be programmed to be accessed only to read data at a high speed, without the need of instruction decoding, in XiP mode (table 2). So, immediately after power up the memory can behave like a random access memory, at the maximum speed allowed by the overall system architecture.  It is also possible to program a single, dual or quad I/O mode, using one, two or four wires in parallel to send/receive data between the microprocessor and the memory. This is sometimes very convenient with microprocessors that can interact with the memory parallelizing the bit flow. In figure 2 an example of XiP mode after power-up. In figures 3, 4 and 5 some examples are shown of commands sent on a four-wire parallel bus.

Furthermore, the power-on time may be reduced by programming the appropriate bit in the non-volatile configuration registers.

 

Cost-efficiency and flexibility

The configuration registers are a powerful tool to adjust the working parameters and conditions of a non-volatile SPI Flash memory in order to find the best fit for any application.

SPI Flash memories have the great advantage of a low pin count that simplifies the board layout, decreases the total system cost and enables very complex solutions.  Moreover, the same protocol and pin configuration can be used for all densities, enabling intrinsic scalability and allowing the connection of different devices to a single bus.  The new generation of SPI Flash memories with configuration registers overcome the typical disadvantages of traditional serial memory solutions, because they allow a great flexibility and open the way to cost-efficient high-speed XiP memory systems.

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Fig.1 – Volatile & Non-volatile configuration register interaction

Fig.2 – XiP mode, Quad I/O fast read operation

Fig.3 – Quad command SPI

Fig.4 – Quad command Fast Read

Fig.5_Quad command Page Program

Tab.1 – NVCR example of Parameter Timing

Tab.2 – Clock cycles saved by mean of XiP modes in any of the available protocols