Home »
Technology News
EU embedded project SPEEDS to conclusion
July 30, 2010 | Colin Holland | 222903037
The four-year SPEEDS (SPEculative
and Exploratory Design in Systems Engineering) project, funded under the
European Union's 6th Framework Programme, has come to a successful
conclusion.
The SPEEDS project has resulted in the definition of a novel end-to-end design methodology, process and tool environment for model-based safety-critical embedded systems that significantly improves design quality while reducing both design cycle times and costs.
The SPEEDS consortium comprises the following companies and research institutions: Airbus, Atego (Extessy), Carmeq, EADS, Esterel Technologies, Dassault Systèmes (Geensoft), IBM Israel, Institut National de Récherche en Informatique et en Automatique (INRIA), Israel Aerospace Industries (IAI), Knorr Bremse Fekrendszerek, Kuratorium OFFIS, Magna Powertrain Engineering Center, Parades Geie, Robert Bosch, Saab and Université Joseph Fourier Grenoble.
"A unique collaboration between embedded systems researchers, developers and design tool vendors, the successful conclusion of the SPEEDS project will substantially improve the competitiveness of the European embedded systems industry," said Gert Döhmen, Coordinator of the SPEEDS Consortium and Head of Processes and Methods, Avionics Platforms and Electrical Systems at Airbus Deutschland.
"SPEEDS provides the basis for the European embedded systems industry to evolve from model-based design of hardware and software systems towards the design and construction of integrated, component-based complete virtual system models."
SPEEDS achieves this by delivering a multi-layered contract-based design and analysis methodology that formalizes the concept of Assumptions and Promises inherent within contracts. A new 'controlled speculative design process' - formalized in the SPEEDS Process Advisor toolset – facilitates trade-off studies through the evaluation of different architectures, enables right-first-time design and minimizes the risk in adopting concurrent design practices.
Building on SysML, the concept of Heterogeneous Rich Components (HRC), in the form of the tool-independent SPEEDS meta-model, underpins the SPEEDS methodology as the basis for model-driven engineering design. The SPEEDS meta-model is expressive enough to cover the complete development cycle from high-level specifications to design models as well as address both functional and non-functional design aspects.
The HRC components are characterized by formal contracts allowing the use of various analysis techniques, including the new concept of hosted simulation, for design validation in the earliest design stages. The SPEEDS meta-model has also been constructed to seamlessly extend the capabilities of existing industry-specific SysML-based meta-models such as AUTOSAR and AADL.
Supporting the SPEEDS methodology is the SPEEDS Tool Architecture. The tool-independence of the SPEEDS meta-model enables the easy integration of any commercially available embedded systems design tool as it avoids the need for file exchange. Design tool integration is built on the defacto Eclipse standard using the SPEEDS Bus for which the API has been published.
The SPEEDS methodology is also real-world proven having been successfully implemented in pilot projects by the SPEEDS user partners utilizing SPEEDS-compliant tools from the project's vendor partners. Over 20 large enterprises are now planning to exploit the methodology and concepts as part of their systems design processes.
"The exploitation of the SPEEDS project results is rapidly gaining momentum through implementation of integrated tool environments," said Dr. Michael Winokur, Technical Manager of the SPEEDS project and Corporate Director of Engineering and Development at Israel Aerospace Industries (IAI).
"This is being achieved through the insertion of the multi-layered contract-based design methodology and its underlying HRC meta-model in the industrial partners' engineering design processes, coupled with the tight support of the tool vendors involved in the project who are keen to commercialize the results by incorporating them in their tool suites," added Dr. Winokur.
For developers wishing to explore the potential benefits of the SPEEDS methodology, a variety of materials have been published and are available for download.
These include the SPEEDS meta-model and implementation guide, HRC Compiler, Contract Specification Language, SPEEDS Lessons and Best Practices guide and a SPEEDS training kit.
The SPEEDS consortium is also working towards the publication of a book that will make the SPEEDS methodology and design process available for widespread industrial use, university courses and technical training for both end users and technology providers.
The SPEEDS consortium comprises the following companies and research institutions: Airbus, Atego (Extessy), Carmeq, EADS, Esterel Technologies, Dassault Systèmes (Geensoft), IBM Israel, Institut National de Récherche en Informatique et en Automatique (INRIA), Israel Aerospace Industries (IAI), Knorr Bremse Fekrendszerek, Kuratorium OFFIS, Magna Powertrain Engineering Center, Parades Geie, Robert Bosch, Saab and Université Joseph Fourier Grenoble.
"A unique collaboration between embedded systems researchers, developers and design tool vendors, the successful conclusion of the SPEEDS project will substantially improve the competitiveness of the European embedded systems industry," said Gert Döhmen, Coordinator of the SPEEDS Consortium and Head of Processes and Methods, Avionics Platforms and Electrical Systems at Airbus Deutschland.
"SPEEDS provides the basis for the European embedded systems industry to evolve from model-based design of hardware and software systems towards the design and construction of integrated, component-based complete virtual system models."
SPEEDS achieves this by delivering a multi-layered contract-based design and analysis methodology that formalizes the concept of Assumptions and Promises inherent within contracts. A new 'controlled speculative design process' - formalized in the SPEEDS Process Advisor toolset – facilitates trade-off studies through the evaluation of different architectures, enables right-first-time design and minimizes the risk in adopting concurrent design practices.
Building on SysML, the concept of Heterogeneous Rich Components (HRC), in the form of the tool-independent SPEEDS meta-model, underpins the SPEEDS methodology as the basis for model-driven engineering design. The SPEEDS meta-model is expressive enough to cover the complete development cycle from high-level specifications to design models as well as address both functional and non-functional design aspects.
The HRC components are characterized by formal contracts allowing the use of various analysis techniques, including the new concept of hosted simulation, for design validation in the earliest design stages. The SPEEDS meta-model has also been constructed to seamlessly extend the capabilities of existing industry-specific SysML-based meta-models such as AUTOSAR and AADL.
Supporting the SPEEDS methodology is the SPEEDS Tool Architecture. The tool-independence of the SPEEDS meta-model enables the easy integration of any commercially available embedded systems design tool as it avoids the need for file exchange. Design tool integration is built on the defacto Eclipse standard using the SPEEDS Bus for which the API has been published.
The SPEEDS methodology is also real-world proven having been successfully implemented in pilot projects by the SPEEDS user partners utilizing SPEEDS-compliant tools from the project's vendor partners. Over 20 large enterprises are now planning to exploit the methodology and concepts as part of their systems design processes.
"The exploitation of the SPEEDS project results is rapidly gaining momentum through implementation of integrated tool environments," said Dr. Michael Winokur, Technical Manager of the SPEEDS project and Corporate Director of Engineering and Development at Israel Aerospace Industries (IAI).
"This is being achieved through the insertion of the multi-layered contract-based design methodology and its underlying HRC meta-model in the industrial partners' engineering design processes, coupled with the tight support of the tool vendors involved in the project who are keen to commercialize the results by incorporating them in their tool suites," added Dr. Winokur.
For developers wishing to explore the potential benefits of the SPEEDS methodology, a variety of materials have been published and are available for download.
These include the SPEEDS meta-model and implementation guide, HRC Compiler, Contract Specification Language, SPEEDS Lessons and Best Practices guide and a SPEEDS training kit.
The SPEEDS consortium is also working towards the publication of a book that will make the SPEEDS methodology and design process available for widespread industrial use, university courses and technical training for both end users and technology providers.
Please login to post your comment - click here
Related News
- Switch mainframes boost system throughput for semiconductor test applications
- Automating the static timing analysis process
- NSF funds computer design variabilty project
- Laser Services expands its capabilities in ceramic materials inventory and laser machining
- CADSTAR update cuts engineering costs
- SynaptiCAD expands WaveFormer coverage
- In-system emulation technology VarioTAP now supports the ARM11 core
- Silicon Labs and Beceem Communications partner on WiMax VOIP gateway reference design
- Actel releases Windows 7 compliant Libero IDE toolset
- Lattice offers improved power optimisation in CPLD design tools
MOST POPULAR NEWS
- Intel seen as likely buyer for Infineon group
- Fuel cell breakthrough aims at commercialization
- Intel to purchase Infineon's Wireless Solutions Business in USD 1.4 billion cash transaction
- AMD unveils two new x86 cores
- Marvell and Harman bring advanced Wi-Fi to the automotive industry
- Apple iPad upgrade likely to get STMicro gyro
- A4 chip drives AppleTV, iPod Touch
- 'Rocking' robot mimics human/ape climbers
- Decision time looms for hard drive makers
- Toshiba spins 2.5 Tbit hard disk
Interview
Technical papers
READER OFFER
The Spartan-6 FPGA embedded kit offered by Xilinx in this month's reader offer is based on the company's Spartan-6 LX45T FPGA. It contains an extensible development board and the key tools and IP needed for embedded development.
The reference designs and software/hardware tutorials provided with this kit will give a jump-start to your development. The package worth 735 Euros includes a ROHS compliant SP605 base board including the XC6SLX45T-FGG484 -3 FPGA, the ISE Design Suite device-locked for the Spartan-6 LX45T FPGA and numerous other tools.
READER OFFER
This month, Xilinx is giving away one such kit, worth 735 Euros, for EETimes Europe's readers to win.
Poll
All material on this site Copyright © 2009 - 2010 European Business Press SA. All rights reserved.
This site contains articles under license from EETimes Group , a division of United Business Media LLC.
This site contains articles under license from EETimes Group , a division of United Business Media LLC.


